xcore port-to-pin mapping#

On xcore devices, pins are used to interface with external components via ports and to construct links to other devices over which channels are established. The ports are multiplexed, allowing the pins to be configured for use by ports of different widths. Available ports and links for each pin gives the XCORE port-to-pin mapping, which is interpreted as follows:

  • The name of each pin is given in the format X<n>D<pq> where n is a valid xCORE Tile number for the device and pq exists in the table. The physical position of the pin depends on the packaging and is given in the device datasheet.

  • Each link is identified by a letter A-D. The wires of a link are identified by means of a superscripted digit 0-4.

  • Each port is identified by its width (the first number 1, 4, 8, 16 or 32) and a letter that distinguishes multiple ports of the same width (A-P). These names correspond to port identifiers in the header file <xs1.h> (for example port 1A corresponds to the identifier XS1_PORT_1A). The individual bits of the port are identified by means of a superscripted digit 0-31.

  • The table is divided into six rows (or banks). The first four banks provide a selection of 1, 4 and 8-bit ports, with the last two banks enabling the single 32-bit port. Different packaging options may export different numbers of banks; the 16-bit and 32-bit ports are not available on small devices.

The ports used by a program are determined by the set of XC port declarations. For example, the declaration:

on tile [0] : in port p = XS1_PORT_1A

uses the 1-bit port 1A on xcore Tile 0, which is connected to pin X0D00.

Usually the designer should ensure that there is no overlap between the pins of the declared ports, but the precedence has been designed so that, if required, portions of the wider ports can be used when overlapping narrower ports are used. The ports to the left of the table have precedence over ports to the right. If two ports are declared that share the same pin, the narrower port takes priority. For example:

on tile[2] : out port p1 = XS1_PORT_32A;
on tile[2] : out port p2 = XS1_PORT_8B;
on tile[2] : out port p3 = XS1_PORT_4C;

In this example:

  • I/O on port p1 uses pins X2D02 to X2D09 and X2D49 to X2D70.

  • I/O on port p2 uses pins X2D16 to X2D19; inputting from p2 results in undefined values in bits 0, 1, 6 and 7.

  • I/O on port p3 uses pins X2D14, X2D15, X2D20 and X2D21; inputting from p1 results in undefined values in bits 28-31, and when outputting these bits are not driven.

Table 56 Available ports and links for each pin#

Highest precedence

Lowest precedence

Pin

link

1-bit ports

4-bit ports

8-bit ports

16-bit ports

32-bit port

XnD00

1A

XnD01

A4 out

1B

XnD02

A3 out

4A0

8A0

16A0

32A20

XnD03

A2 out

4A1

8A1

16A1

32A21

XnD04

A1 out

4B0

8A2

16A2

32A22

XnD05

A0 out

4B1

8A3

16A3

32A23

XnD06

A0 in

4B2

8A4

16A4

32A24

XnD07

A1 in

4B3

8A5

16A5

32A25

XnD08

A2 in

4A2

8A6

16A6

32A26

XnD09

A3 in

4A3

8A7

16A7

32A27

XnD10

A4 in

1C

XnD11

1D

XnD12

1E

XnD13

B4 out

1F

XnD14

B3 out

4C0

8B0

16A8

32A28

XnD15

B2 out

4C1

8B1

16A9

32A29

XnD16

B1 out

4D0

8B2

16A10

XnD17

B0 out

4D1

8B3

16A11

XnD18

B0 in

4D2

8B4

16A12

XnD19

B1 in

4D3

8B5

16A13

XnD20

B2 in

4C2

8B6

16A14

32A30

XnD21

B3 in

4C3

8B7

16A15

32A31

XnD22

B4 in

1G

XnD23

1H

XnD24

1I

XnD25

1J

XnD26

4E0

8C0

16B0

XnD27

4E1

8C1

16B1

XnD28

4F0

8C2

16B2

XnD29

4F1

8C3

16B3

XnD30

4F2

8C4

16B4

XnD31

4F3

8C5

16B5

XnD32

4E2

8C6

16B6

XnD33

4E3

8C7

16B7

XnD34

1K

XnD35

1L

XnD36

1M

8D0

16B8

XnD37

1N

8D1

16B9

XnD38

1O

8D2

16B10

XnD39

1P

8D3

16B11

XnD40

8D4

16B12

XnD41

8D5

16B13

XnD42

8D6

16B14

XnD43

8D7

16B15

XnD49

C4 out

32A0

XnD50

C3 out

32A1

XnD51

C2 out

32A2

XnD52

C1 out

32A3

XnD53

C0 out

32A4

XnD54

C0 in

32A5

XnD55

C1 in

32A6

XnD56

C2 in

32A7

XnD57

C3 in

32A8

XnD58

C4 in

32A9

XnD61

D4 out

32A10

XnD62

D3 out

32A11

XnD63

D2 out

32A12

XnD64

D1 out

32A13

XnD65

D0 out

32A14

XnD66

D0 in

32A15

XnD67

D1 in

32A16

XnD68

D2 in

32A17

XnD69

D3 in

32A18

XnD70

D4 in

32A19