Device Interfaces#
The XVF3800 supports a range of interfaces which allows the device to be integrated into multiple applications.
Audio Interfaces#
Audio Master Clock (MCLK)#
The XVF3800 uses a master audio clock (MCLK) to drive the internal pipeline processing.
The MCLK signal can be derived one of two sources.
1 - Internal MCLK
The MCLK signal is generated internally in the XVF3800 using a Phase Locked Loop (PLL) that uses the I2S clock or USB frame clock as the timing reference.
Signal |
Description |
Comment |
Pin |
I/O |
---|---|---|---|---|
MCLK_INOUT |
Master audio clock output |
Output - Connect to pin 41 |
14 |
O |
MCLK |
Master audio clock |
Connect to pin 14 |
41 |
I |
I2S_BCLK |
I2S bit synchronisation clock |
Configurable for 16 kHz (1.024 MHz) and 48 kHz (3.072 MHz) sample rates |
13 |
I |
I2S_LRCK |
I2S Left/Right clock |
10 |
I |
Note
This mode is the only clock mode supported in the UA configurations. The audio output stream provides the reference signal for the internal PLL.
2 - External MCLK
The host system can supply a master clock to the XVF3800. This signal must be synchronised to the I2S clock for correct operation. A 12.288 MHz clock frequency is recommended, but this can be modified in the system firmware if required.
Signal |
Description |
Comment |
Pin |
I/O |
---|---|---|---|---|
MCLK_INOUT |
Master audio clock input |
14 |
I |
|
MCLK |
Master audio clock |
Connected to pin 14 |
41 |
I |
Note
The XVF3800 requires 32b clocks per sample on the I2S interface.
PDM Microphone Inputs#
Four standard PDM MEMS microphones should be connected to the MIC_DATA[0..3] pins. The XVF3800 outputs a clock at 3.072 MHz on the MIC_CLK output, which must be fed directly to all microphones. This clock is derived from the MLCK and must be used to clock the microphone PDM output to avoid undefined artefacts in the processed audio stream.
The XVF3800 voice processor has been tested and characterised with microphones in a linear array placed with a 33 mm separation and a square array with a 66 mm spacing. Other spacings with a maximum spacing of 100 mm are possible, but uncharacterised.
These microphones should be connected to the product enclosure in such a way that the acoustic path to each microphone from outside the product is independent. The XVF3800 algorithms are configured as part of the firmware build configuration.
Audio Interface#
The XVF3800 supports a flexible set of audio interface types. The specific interfaces of a device is set by the configuration chosen when the firmware image is built.
In INT-Device configurations the XVF3800 operates as an I2S slave receiving a reference audio signal from the host and returning processed microphone signals to the host. This bidirectional flow of audio samples must be synchronised to a single set of I2S clocks, see the table below:
Signal |
Description |
Comment |
Pin |
I/O |
---|---|---|---|---|
MCLK |
Master audio clock |
14 |
I/O |
|
I2S_BCLK |
I2S bit synchronisation clock |
Configurable for 16 kHz (1.024 MHz) and 48 kHz (3.072 MHz) sample rates |
13 |
I |
I2S_LRCK |
I2S Left/Right clock |
48 kHz or 16 kHz clock derived as I2S_BLCK/64 |
10 |
I |
I2S_DATA0 |
I2S Data In |
Reference audio data from I2S device |
9 |
I |
I2S_DATA1 |
I2S Data Out |
Audio data out to host processor |
39 |
O |
I2S_DATA2 |
I2S Data Out |
Audio data out to DAC |
53 |
O |
The I2S audio samples are transmitted serially with a delay of one I2S_BCLK cycle between the change of I2S_LRCK phase and the start (MSB) of the audio sample for that channel. This the standard alignment for I2S systems.
In UA configurations the audio signals to and from the host system are carried over a USB connection. The XVF3800 operates in USB Adaptive Mode to synchronise with the host. In this configuration the I2S interface operates in master mode to supply the far end audio signal to the DAC driving the speaker.
Signal |
Description |
Comment |
Pin |
I/O |
---|---|---|---|---|
MCLK |
Master audio clock |
14 |
I/O |
|
I2S_BCLK |
I2S bit synchronisation clock |
Configurable for 16 kHz (1.024 MHz) and 48 kHz (3.072 MHz) sample rates |
13 |
O |
I2S_LRCK |
I2S Left/Right clock |
48 kHz or 16 kHz clock derived as I2S_BLCK/64 |
10 |
O |
I2S_DATA0 |
I2S Data Out |
Audio data out to DAC |
9 |
O |
I2S_DATA1 |
I2S Data In |
Optional reference audio data in |
39 |
I |
Integrated USB Interface#
The XVF3800 includes an integrated USB 2.0 PHY supporting Audio Class 2.0 running at High Speed (480 Mbps). This interface is used by the USB host to output a far end signal to a DAC and loudspeaker, to receive processed microphone signals from the XVF3800 audio pipeline and to allow the host to control the operation of the device. In this mode the adaptive USB Audio endpoint is used to generate an MCLK synchronised to the USB host output stream rate. This is provided via the MCLK output on the device. In the case of no output stream being available, the MLCK output is set to a nominal 12.288 MHz.
The table below shows the signals required to implement a USB interface using the XVF3800.
Name |
Description |
Pin |
---|---|---|
USB_DP |
Connect to USB connector |
29 |
USB_DM |
Connect to USB connector |
28 |
USB_VBUS _DET |
Do not connect Self-powered operation is not supported by current device firmware |
43 |
USB_VDD18 |
1.8V supply for USB-PHY - May be left floating if the USB interface is not used |
31 |
USB_VDD33 |
3.3V supply to the USB-PHY May be left floating if the USB interface is not used |
30 |
System firmware#
QSPI Boot Mode#
When QSPI boot mode is enabled (default), the XVF3800 enables six QSPI pins and drives the QSPI clock as a QSPI Master.
For further information about the boot sequence refer to the XU316-1024-QF60B datasheet.
Host boot via SPI#
The SPI interface can be utilised by a host controller to download the XVF3800 firmware to boot the device. Details of the SPI boot protocol can be found in the XVF3800 User Guide.
To enable the SPI boot from an external host processor, the QSPI_D1/BOOTSEL should be pulled to VDDIO on power-up. This activates the SPI interface, which operates as a slave to the host processor for the transfer of the boot image, which is clocked in with the least significant bit first in each transferred byte.
This is an alternative to using an attached QSPI flash to automatically transfer boot data on start-up.
The SPI pins are shown in the table below.
Signal |
Description |
Comment |
Pin |
I/O |
---|---|---|---|---|
SPI_CLK |
SPI Clock |
5 |
I |
|
SPI_CS_N |
SPI Chip Select |
Pull high externally to the device using a 4.7k ohm resistor |
6 |
I |
SPI_MOSI |
SPI Master Out Slave In |
7 |
I |
|
SPI_MISO |
SPI Master In Slave Out |
May be left floating if not required |
47 |
O |
Device Control Interface#
The XVF3800 has a control framework that can be used to update device parameters and read data from the audio pipeline and the I/O pins.
Three protocols options are supported - USB, SPI or I2C. The protocol is set as a compile time option when the firmware image is built. Only one protocol can be active in a specific configuration, but the same control commands are available via all interface types.
Warning
Some commands have no effect on device operation if they are not valid for the configuration in use.
A host control application is provided in the firmware release package that implements the control protocol and provides a user interface for the XVF3800 device.
Note
Only one control protocol, USB, SPI or I2C can be used in a specific implementation. This choice is set in the firmware and cannot be changed during operation of the device.
USB Control Interface#
In the UA configuration of the XVF3800, the control interface is available via the USB Endpoint 0.
I2C Control Interface#
The I2C slave interface is used to control and configure the parameters on the XVF3800.
The interface operates with the following specifications:
100 kbps SCL clock speed
Register read/write
Up to 60 byte I2C read/write
The device I2C address is 0x2C, and the pin connections are shown below.
Signal |
Description |
Comment |
Pin |
I/O |
---|---|---|---|---|
I2C_SCL |
I2C serial clock line for receiving control command from I2C host |
44 |
I/O |
|
I2C_SDA |
I2C serial data line for receiving control command from I2C host |
45 |
I/O |
SPI Control Interface#
The SPI slave interface can used to control and configure the parameters on the XVF3800.
Note
Only one control protocol, SPI or I2C can be used in a specific implementation. This choice is set in the firmware and cannot be changed while the device is operating.
For more information on control and configuration of the XVF3800 please refer to the User Guide.
General Purpose Input/Output#
Two input and five output pins are provided to allow general-purpose I/O (GPIO) such as LEDs and button controls. Input pins can be individually read by the host using the control interface and configured to detect edge events. The output pins can be individually set, and they have configurable Pulse Width Modulated (PWM) brightness control with blinking sequences.
The INT_N pin provides a hardware interrupt to the host system to indicate if a GPI has been triggered. The behaviour of this pin, e.g. which GPI, which edge etc, can be configured in via the control interface.
The standard allocation of the GPIO pins in the XK-VOICE-SQ66 development kit is shown in the table below, but these can be adapted in the device firmware for other uses if required for a specific design.
Name |
Description |
Pin |
I/O |
---|---|---|---|
P_BUTTON_0 |
Input for ‘Mute’ button |
11 |
I |
P_BUTTON_1 |
Input for ‘Action’ button |
32 |
I |
CODEC_RST_N |
GPO for driving reset of conected DAC or digital amplifier |
40 |
O |
SQ_nLIN |
GPO for selecting topology mode of mics |
54 |
O |
INT_N |
GPO for signalling an interrupt to the host |
55 |
O |
LED_R |
Red element of tri-colour LED |
56 |
O |
LED_G |
Green element of tri-colour LED |
57 |
O |
For more information on configuring these inputs and outputs, please refer to the XVF3800 User Guide.