XS1 port-to-pin mapping

On XS1 devices, pins are used to interface with external components via ports and to construct links to other devices over which channels are established. The ports are multiplexed, allowing the pins to be configured for use by ports of different widths. Available ports and links for each pingives the XS1 port-to-pin mapping, which is interpreted as follows:

• The name of each pin is given in the format XnDpq where n is a valid xCORE Tile number for the device and pq exists in the table. The physical position of the pin depends on the packaging and is given in the device datasheet.
• Each link is identified by a letter A-D. The wires of a link are identified by means of a superscripted digit 0-4.
• Each port is identified by its width (the first number 1, 4, 8, 16 or 32) and a letter that distinguishes multiple ports of the same width (A-P). These names correspond to port identifiers in the header file<xs1.h> (for example port 1A corresponds to the identifierXS1_PORT_1A). The individual bits of the port are identified by means of a superscripted digit 0-31.
• The table is divided into six rows (or banks). The first four banks provide a selection of 1, 4 and 8-bit ports, with the last two banks enabling the single 32-bit port. Different packaging options may export different numbers of banks; the 16-bit and 32-bit ports are not available on small devices.

The ports used by a program are determined by the set of XC port declarations. For example, the declaration

on tile [0] : in port p = XS1_PORT_1A

uses the 1-bit port 1A on xCORE Tile 0, which is connected to pin X0D00.

Usually the designer should ensure that there is no overlap between the pins of the declared ports, but the precedence has been designed so that, if required, portions of the wider ports can be used when overlapping narrower ports are used. The ports to the left of the table have precedence over ports to the right. If two ports are declared that share the same pin, the narrower port takes priority. For example:

on tile[2] : out port p1 = XS1_PORT_32A;

on tile[2] : out port p2 = XS1_PORT_8B;

on tile[2] : out port p3 = XS1_PORT_4C;

In this example:

Available ports and links for each pin

Documentation