11 #ifndef TRC_HARDWARE_PORT_H
12 #define TRC_HARDWARE_PORT_H
14 #include <trcDefines.h>
21 #define TRACE_ALLOC_CRITICAL_SECTION_NAME xTraceCriticalSectionStatus
23 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
24 #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
96 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
97 #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
100 #if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32)
102 void vTraceTimerReset(
void);
103 uint32_t uiTraceTimerGetFrequency(
void);
104 uint32_t uiTraceTimerGetValue(
void);
106 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
107 #define TRC_HWTC_COUNT ((TraceUnsignedBaseType_t)uiTraceTimerGetValue())
108 #define TRC_HWTC_PERIOD 0
109 #define TRC_HWTC_DIVISOR 1
110 #define TRC_HWTC_FREQ_HZ ((TraceUnsignedBaseType_t)uiTraceTimerGetFrequency())
112 #define TRC_IRQ_PRIORITY_ORDER 1
114 #define TRC_PORT_SPECIFIC_INIT() vTraceTimerReset()
116 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win64)
118 void vTraceTimerReset(
void);
119 uint32_t uiTraceTimerGetFrequency(
void);
120 uint32_t uiTraceTimerGetValue(
void);
122 #define TRC_BASE_TYPE int64_t
124 #define TRC_UNSIGNED_BASE_TYPE uint64_t
126 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
127 #define TRC_HWTC_COUNT ((TraceUnsignedBaseType_t)uiTraceTimerGetValue())
128 #define TRC_HWTC_PERIOD 0
129 #define TRC_HWTC_DIVISOR 1
130 #define TRC_HWTC_FREQ_HZ ((TraceUnsignedBaseType_t)uiTraceTimerGetFrequency())
132 #define TRC_IRQ_PRIORITY_ORDER 1
134 #define TRC_PORT_SPECIFIC_INIT() vTraceTimerReset()
136 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent)
138 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
139 #define TRC_HWTC_COUNT 0
140 #define TRC_HWTC_PERIOD 1
141 #define TRC_HWTC_DIVISOR 1
142 #define TRC_HWTC_FREQ_HZ TRC_TICK_RATE_HZ
145 #define TRC_IRQ_PRIORITY_ORDER NOT_SET
147 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M)
150 #error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h"
153 #define TRACE_ALLOC_CRITICAL_SECTION() uint32_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
154 #define TRACE_ENTER_CRITICAL_SECTION() {TRACE_ALLOC_CRITICAL_SECTION_NAME = __get_PRIMASK(); __set_PRIMASK(1);}
155 #define TRACE_EXIT_CRITICAL_SECTION() {__set_PRIMASK(TRACE_ALLOC_CRITICAL_SECTION_NAME);}
167 #if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK))
169 void xTraceHardwarePortInitCortexM(
void);
171 #define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC)
172 #define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000)
173 #define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004)
174 #define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C)
176 #define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0)
177 #define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55)
180 #define TRC_DEMCR_TRCENA (1 << 24)
183 #define TRC_DWT_CTRL_NOPRFCNT (1 << 24)
186 #define TRC_DWT_CTRL_NOCYCCNT (1 << 25)
189 #define TRC_DWT_CTRL_EXCEVTENA (1 << 18)
192 #define TRC_DWT_CTRL_CYCCNTENA (1)
194 #define TRC_PORT_SPECIFIC_INIT() xTraceHardwarePortInitCortexM()
196 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
197 #define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT
198 #define TRC_HWTC_PERIOD 0
199 #define TRC_HWTC_DIVISOR 4
200 #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
201 #define TRC_IRQ_PRIORITY_ORDER 0
205 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
206 #define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018))
207 #define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1)
208 #define TRC_HWTC_DIVISOR 4
209 #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
210 #define TRC_IRQ_PRIORITY_ORDER 0
214 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600)
215 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
216 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); }
217 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
219 #include <iodefine.h>
221 #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
223 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
224 #define TRC_HWTC_COUNT (CMT0.CMCNT)
226 #elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)
229 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
230 #define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT)
234 #define TRC_HWTC_PERIOD (CMT0.CMCOR + 1)
235 #define TRC_HWTC_DIVISOR 1
236 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
237 #define TRC_IRQ_PRIORITY_ORDER 1
239 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32)
241 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
242 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); }
243 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
245 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
246 #define TRC_HWTC_COUNT (TMR1)
247 #define TRC_HWTC_PERIOD (PR1 + 1)
248 #define TRC_HWTC_DIVISOR 1
249 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
250 #define TRC_IRQ_PRIORITY_ORDER 1
252 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48)
254 #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)
255 #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)
256 #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)
258 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
259 #define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
260 #define TRC_HWTC_PERIOD (TRC_RTIUDCP0)
261 #define TRC_HWTC_DIVISOR 1
262 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
263 #define TRC_IRQ_PRIORITY_ORDER 0
265 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7)
269 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
270 #define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
271 #define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
272 #define TRC_HWTC_DIVISOR 1
273 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
274 #define TRC_IRQ_PRIORITY_ORDER 1
276 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0)
282 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
283 #define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
284 #define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
285 #define TRC_HWTC_DIVISOR 1
286 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
287 #define TRC_IRQ_PRIORITY_ORDER 1
289 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X)
295 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
296 #define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 )
297 #define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 )
298 #define TRC_HWTC_DIVISOR 1
299 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
300 #define TRC_IRQ_PRIORITY_ORDER 0
302 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430)
306 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
307 #define TRC_HWTC_COUNT (TA0R)
308 #define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1)
309 #define TRC_HWTC_DIVISOR 1
310 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
311 #define TRC_IRQ_PRIORITY_ORDER 1
313 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405)
317 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
318 #define TRC_HWTC_COUNT mfspr(0x3db)
319 #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRC_TICK_RATE_HZ)
320 #define TRC_HWTC_DIVISOR 1
321 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
322 #define TRC_IRQ_PRIORITY_ORDER 0
324 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440)
330 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
331 #define TRC_HWTC_COUNT mfspr(0x016)
332 #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRC_TICK_RATE_HZ)
333 #define TRC_HWTC_DIVISOR 1
334 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
335 #define TRC_IRQ_PRIORITY_ORDER 0
337 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE)
345 #include <xtmrctr_l.h>
347 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
348 #define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
349 #define TRC_HWTC_PERIOD (XTmrCtr_GetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
350 #define TRC_HWTC_DIVISOR 16
351 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
352 #define TRC_IRQ_PRIORITY_ORDER 0
354 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5)
356 extern int cortex_a9_r5_enter_critical(
void);
357 extern void cortex_a9_r5_exit_critical(
int irq_already_masked_at_enter);
359 #define TRACE_ALLOC_CRITICAL_SECTION() uint32_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
361 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
363 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
365 #include <xttcps_hw.h>
367 #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
368 #define TRC_HWTC_COUNT (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_COUNT_VALUE_OFFSET))
369 #define TRC_HWTC_PERIOD (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_INTERVAL_VAL_OFFSET))
370 #define TRC_HWTC_DIVISOR 16
371 #define TRC_HWTC_FREQ_HZ (TRC_HWTC_PERIOD * TRC_TICK_RATE_HZ)
372 #define TRC_IRQ_PRIORITY_ORDER 0
376 static inline uint32_t prvGetCPSR(
void)
380 asm volatile (
" mrs %0, cpsr" :
"=r" (ret) : );
384 #error "Only GCC Supported!"
387 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII)
392 #include <altera_avalon_timer_regs.h>
393 #include <sys/alt_irq.h>
395 #define TRACE_ALLOC_CRITICAL_SECTION() alt_irq_context TRACE_ALLOC_CRITICAL_SECTION_NAME;
396 #define TRACE_ENTER_CRITICAL_SECTION(){TRACE_ALLOC_CRITICAL_SECTION_NAME = alt_irq_disable_all();}
397 #define TRACE_EXIT_CRITICAL_SECTION() {alt_irq_enable_all(TRACE_ALLOC_CRITICAL_SECTION_NAME);}
405 #define SYSTEM_TIMER_BASE NOT_SET
407 #if (SYSTEM_TIMER == NOT_SET)
408 #error "Set SYSTEM_TIMER_BASE to the timer base used for system ticks."
411 static inline uint32_t altera_nios2_GetTimerSnapReg(
void)
416 IOWR_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE, 0);
417 return (IORD_ALTERA_AVALON_TIMER_SNAPH(SYSTEM_TIMER_BASE) << 16) | IORD_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE);
420 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
421 #define TRC_HWTC_COUNT altera_nios2_GetTimerSnapReg()
422 #define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ )
423 #define TRC_HWTC_DIVISOR 16
424 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
425 #define TRC_IRQ_PRIORITY_ORDER 0
427 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)
446 extern int cortex_a9_r5_enter_critical(
void);
447 extern void cortex_a9_r5_exit_critical(
int irq_already_masked_at_enter);
449 #define TRACE_ALLOC_CRITICAL_SECTION() uint32_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
450 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
451 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
454 #define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0
456 #if (TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS == 0)
457 #error "Please specify TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS."
460 #define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600
461 #define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00))
462 #define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04))
463 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08))
465 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
466 #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
467 #define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
469 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
470 #define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG
471 #define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1)
479 #define TRC_HWTC_DIVISOR 1
481 #define TRC_HWTC_FREQ_HZ (TRC_TICK_RATE_HZ * TRC_HWTC_PERIOD)
482 #define TRC_IRQ_PRIORITY_ORDER 0
486 static inline uint32_t prvGetCPSR(
void)
490 asm volatile (
" mrs %0, cpsr" :
"=r" (ret) : );
494 #error "Only GCC Supported!"
497 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_CYCLONE_V_HPS)
498 #include "alt_clock_manager.h"
500 extern int cortex_a9_r5_enter_critical(
void);
501 extern void cortex_a9_r5_exit_critical(
int irq_already_masked_at_enter);
503 #define TRACE_ALLOC_CRITICAL_SECTION() uint32_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
504 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = cortex_a9_r5_enter_critical(); }
505 #define TRACE_EXIT_CRITICAL_SECTION() { cortex_a9_r5_exit_critical(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
507 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
508 #define TRC_HWTC_COUNT *((uint32_t *)0xFFFEC200)
509 #define TRC_HWTC_PERIOD 0
510 #define TRC_HWTC_DIVISOR 1
511 #define TRC_HWTC_FREQ_HZ (({ \
513 alt_clk_freq_get( ALT_CLK_MPU_PERIPH, &__freq ); \
516 #define TRC_IRQ_PRIORITY_ORDER 0
520 static inline uint32_t prvGetCPSR(
void)
524 __asm__ __volatile__(
" mrs %0, cpsr" :
"=r" (ret) : );
528 #error "Only GCC Supported!"
531 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ZEPHYR)
532 #define TRACE_ALLOC_CRITICAL_SECTION() int TRACE_ALLOC_CRITICAL_SECTION_NAME;
533 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = irq_lock(); }
534 #define TRACE_EXIT_CRITICAL_SECTION() { irq_unlock(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
536 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
537 #define TRC_HWTC_COUNT k_cycle_get_32()
538 #define TRC_HWTC_PERIOD (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
539 #define TRC_HWTC_DIVISOR 4
540 #define TRC_HWTC_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
541 #define TRC_IRQ_PRIORITY_ORDER 0 // Lower IRQ priority values are more significant
543 #define TRC_PORT_SPECIFIC_INIT()
545 #elif ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XTensa_LX6) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XTensa_LX7))
550 #if CONFIG_FREERTOS_UNICORE == 1
551 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
552 #define TRC_HWTC_COUNT ({ unsigned int __ccount; \
553 __asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
555 #ifdef CONFIG_IDF_TARGET_ESP32
556 #define TRC_HWTC_FREQ_HZ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
557 #elif defined(CONFIG_IDF_TARGET_ESP32S2)
558 #define TRC_HWTC_FREQ_HZ (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000)
560 #error "Invalid IDF target, check your sdkconfig."
562 #define TRC_HWTC_PERIOD 0
563 #define TRC_HWTC_DIVISOR 4
564 #define TRC_IRQ_PRIORITY_ORDER 0
572 uint32_t prvGetSMPTimestamp();
574 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
575 #define TRC_HWTC_COUNT prvGetSMPTimestamp()
576 #define TRC_HWTC_FREQ_HZ 40000000
577 #define TRC_HWTC_PERIOD 0
578 #define TRC_HWTC_DIVISOR 4
579 #define TRC_IRQ_PRIORITY_ORDER 0
582 #if !defined(TRC_HWTC_FREQ_HZ)
583 #error "The XTensa LX6/LX7 trace hardware clock frequency is not defined."
586 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_RISCV_RV32I)
587 #define TRACE_ALLOC_CRITICAL_SECTION() unsigned int TRACE_ALLOC_CRITICAL_SECTION_NAME;
588 #define TRACE_ENTER_CRITICAL_SECTION() __asm__ __volatile__("csrr %0, mstatus \n\t" \
589 "csrci mstatus, 8 \n\t" \
590 "andi %0, %0, 8 \n\t" \
591 : "=r"(TRACE_ALLOC_CRITICAL_SECTION_NAME))
592 #define TRACE_EXIT_CRITICAL_SECTION() __asm__ __volatile__("csrr a1, mstatus \n\t" \
593 "or %0, %0, a1 \n\t" \
594 "csrs mstatus, %0 \n\t" \
596 : "r" (TRACE_ALLOC_CRITICAL_SECTION_NAME) \
598 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
599 #define TRC_HWTC_COUNT ({ unsigned int __count; \
600 __asm__ __volatile__("rdcycle %0" : "=r"(__count)); \
602 #define TRC_HWTC_PERIOD 0
603 #define TRC_HWTC_DIVISOR 1
604 #define TRC_HWTC_FREQ_HZ 16000000
605 #define TRC_IRQ_PRIORITY_ORDER 0
607 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XMOS_XCOREAI)
608 #define TRC_PORT_SPECIFIC_INIT()
609 #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
610 #define TRC_HWTC_COUNT xscope_gettime()
611 #define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ )
612 #define TRC_HWTC_DIVISOR 4
613 #define TRC_HWTC_FREQ_HZ 100000000
614 #define TRC_IRQ_PRIORITY_ORDER 0
616 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4)
620 #define TRACE_ALLOC_CRITICAL_SECTION() TraceBaseType_t TRACE_ALLOC_CRITICAL_SECTION_NAME;
621 #define TRACE_ENTER_CRITICAL_SECTION() { TRACE_ALLOC_CRITICAL_SECTION_NAME = TRC_KERNEL_PORT_SET_INTERRUPT_MASK(); }
622 #define TRACE_EXIT_CRITICAL_SECTION() { TRC_KERNEL_PORT_CLEAR_INTERRUPT_MASK(TRACE_ALLOC_CRITICAL_SECTION_NAME); }
624 #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
626 #define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R // must be the PIT channel used for the systick
627 #define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U) // TODO FIXME or maybe not -1? what's the right "period" value?
628 #define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ
629 #define TRC_HWTC_DIVISOR 1
630 #define TRC_IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
632 #elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED)
634 #if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) )
635 #error "The hardware port is not completely defined!"
638 #elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
640 #error "TRC_CFG_HARDWARE_PORT had unsupported value!"
641 #define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET
645 #ifndef TRC_HWTC_DIVISOR
646 #define TRC_HWTC_DIVISOR 1
649 #ifndef TRC_PORT_SPECIFIC_INIT
650 #define TRC_PORT_SPECIFIC_INIT()
657 #define _WIN32_WINNT 0x0600
669 #define WIN32_PORT_SAVE_WHEN_STOPPED 1
670 #define WIN32_PORT_EXIT_WHEN_STOPPED 1
674 #if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
676 #ifndef TRC_HWTC_TYPE
677 #error "TRC_HWTC_TYPE is not set!"
680 #ifndef TRC_HWTC_COUNT
681 #error "TRC_HWTC_COUNT is not set!"
684 #ifndef TRC_HWTC_PERIOD
685 #error "TRC_HWTC_PERIOD is not set!"
688 #ifndef TRC_HWTC_DIVISOR
689 #error "TRC_HWTC_DIVISOR is not set!"
692 #ifndef TRC_IRQ_PRIORITY_ORDER
693 #error "TRC_IRQ_PRIORITY_ORDER is not set!"
694 #elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1)
695 #error "TRC_IRQ_PRIORITY_ORDER has bad value!"
698 #if (TRC_HWTC_DIVISOR < 1)
699 #error "TRC_HWTC_DIVISOR must be a non-zero positive value!"
702 #ifndef TRC_HWTC_FREQ_HZ
703 #error "TRC_HWTC_FREQ_HZ not defined!"
708 #ifndef TRACE_ALLOC_CRITICAL_SECTION
709 #define TRACE_ALLOC_CRITICAL_SECTION() TRC_KERNEL_PORT_ALLOC_CRITICAL_SECTION()
711 #ifndef TRACE_ENTER_CRITICAL_SECTION
712 #define TRACE_ENTER_CRITICAL_SECTION() TRC_KERNEL_PORT_ENTER_CRITICAL_SECTION()
714 #ifndef TRACE_EXIT_CRITICAL_SECTION
715 #define TRACE_EXIT_CRITICAL_SECTION() TRC_KERNEL_PORT_EXIT_CRITICAL_SECTION()