Device Operation#

Electrical and Thermal Characteristics#

For electrical and thermal characteristics, including Absolute Maximum ratings please refer to the XU316-1024-QF60B datasheet.

Power Supplies#

The XVF3800 has the following power supply pins:

Table 12 XVF3800 power pins#
Name	Description	Pin
VDD	Digital core power supply. 0.9 V (nominal)	4 12 19 27 34 42 49 57 61 62 63 64
V_DDIOL	Digital I/O power supply. 3.3 V (nominal)	8
V_DDIOR	Digital I/O power supply. 3.3 V (nominal)	38
V_DDIOT	Digital I/O power supply. 3.3 V (nominal)	52
VDD_IOB18	Digital I/O power supply. 1.8 V (nominal)	17 26
PLL_AVDD	PLL analogue power. This 0.9 V (nominal) PLL supply should be separated from the other supplies at the same voltage by a low pass filter	22
USB_VDD18	Digital supply to the USB-PHY. 1.8 V (nominal)	31
USB_VDD33	Analogue supply to the USB-PHY. 3.3 V (nominal)	30
VSS	Device Ground	65 (Paddle)

Note

A: All VDD power pins must be connected.

B: USB_VDDxx supplies can be left floating if USB is not used.

Clocks#

The XVF3800 device has an on-chip oscillator. To use the oscillator, you need to connect a crystal, two capacitors, and damping and feedback resistors to the device as shown below.

Table 13 XVF3800 crystal oscillator#
Signal	Description	Comment	Pin	I/O
XIN	Crystal oscillator input		16	I
XOUT	Crystal oscillator output		15	O

../../../../_images/image11.png — Fig. 6 Crystal oscillator or clock input configurations#

Alternatively, the XVF3800 can be provided with a 24 MHz, 1V8 clock input on the XIN pin. The clock must be running when the chip comes out of reset.

Table 14 XVF3800 clock signals#
Signal	Description	Comment	Pin	I/O
XIN	Master clock (system)	24 MHz 1V8 clock signal	16	I
XOUT	N/C	Leave floating if clock input on XIN	15	O

Reset#

The XVF3800 device has an on-chip Power-on-Reset (POR). This keeps the chip in reset whilst the supplies are coming up.

See XU316-1024-QF60B datasheet for further information.

Table 15 Reset signal#
Signal	Description	Comment	Pin	I/O
RST_N	Device reset	Active low	21	I

Boot Modes#

On start-up and after a reset event, the XVF3800 is booted either using an externally connected QSPI flash memory or by transferring a boot image to the device via SPI from a host processor.

Slave Boot Mode#

The boot mode is specified using QSPI_D1/BOOTSEL. If this pin is tied high via a 4.7k ohm resistor on start-up, the XVF3800 will enable SPI slave boot mode and activate the pins shown below.

Table 16 SPI slave boot pins#
Signal	Description	Comment	Pin	I/O
QSPI_CLK / SPI_CLK	SPI Clock		5	I
SPI_CS_N	SPI Chip Select	Pull high externally to the device using a 4.7k ohm resistor	6	I
SPI_MOSI	SPI Master Out Slave In		7	I
SPI_MISO	SPI Master In Slave Out		47	O

QSPI Master Boot Mode#

If the QSPI_D1/BOOTSEL pin is connected to a QSPI_D1 pin on a flash device, the XVF3800 will boot from a local QSPI flash in QSPI master mode. The active pins are shown below.

Table 17 QSPI master peripheral interface pins#
Name	Description	Pin	I/O
QSPI_CS_N	QSPI Chip Select. This pin should be pulled high externally to the device using a 4.7k ohm resistor	3	I/O
QSPI_D0	QSPI Data Line 0	59	I/O
QSPI_D1 / BOOTSEL	QSPI Data Line 1 and boot selection. To activate QSPI master boot mode connect directly to QSPI Data Line 1 on Quad capable flash device	1	I/O
QSPI_D2	QSPI Data Line 2	60	I/O
QSPI_D3	QSPI Data Line 3	2	I/O
QSPI_CLK / SPI_CLK	QSPI Clock and SPI Clock	5	I/O

A READ command is issued with a 24-bit address 0x000000. The XVF3800 expects each byte to be transferred with the least-significant nibble first. Programmers that write bytes into a QSPI interface using the most significant nibble first may have to reverse the nibbles in each byte of the image stored in the QSPI device. When bulk programming flash devices the Quad Enable bit in the flash setting register should be set.

QSPI Flash Support#

When a flash memory device is used to store the firmware for the XVF3800, the minimum storage space required is 2 Mbytes.

Flash devices with the following specifications are supported by the XVF3800 (e.g. Winbond W25Q16JWSNIM).

Table 18 Flash device specification supported by XVF3800#
Device characteristic	Description	Value
Page size	Size of flash page in bytes	256
Number of pages	Total number of pages	8192
Address size	Number of bytes used to represent the address	3
Read ID operation code	Operation code to read the device identification (ID) information	0x9F
Read ID dummy bytes	Number of dummy bytes after read command before ID is returned	0
ID size	Size of ID in bytes	3
Sector Erase operation code	Operation code for 4 kB Erase	0x20
Sector information	Arrangement of sectors	Regular (all equally sized - 4 kB)
Write Enable operation code	Operation code for write enable	0x06
Write Disable operation code	Operation code for write disable	0x04
Page Program operation code	Operation code for page program	0x02
Fast Quad Read operation code	Operation code for Fast Quad I/O Read	0xEB
Fast Quad Read Dummy Bytes	Number of dummy bytes after setup of fast quad read that data is returned	1
Read Status Register operation code	Operation code for reading status register	0x05
Write Status Register operation code	Operation code for write to the status register	0x01
Write Status Register Busy Mask	Bit mask for operation in progress (device busy)	0x01

Device Firmware Upgrade (DFU)#

Device Firmware Upgrade (DFU) over USB and I²C is supported for devices that have QSPI flash connected and loaded with a firmware image.

The DFU over USB supports the standard USB DFU class, and it makes use of publicly available host applications.

The DFU over I²C makes use of the same procedures and a similar protocol as the USB DFU, but the host application is XMOS proprietary.

If the DFU process fails, the boot process falls back to the factory image allowing the user to re-attempt the upgrade. Images loaded via DFU can also be removed allowing the device to revert to the factory image.

The factory image is loaded only after a reboot of the device, either via the DFU host application or by powering the device off and on.

For further information on the operation of the DFU mechanism refer to the XVF3800 User Guide.