Sample Rate Conversion Library

• Conversion between 44.1, 48, 88.2, 96, 176.4 and 192KHz input and output sample rates
• 32 bit PCM input and output data in Q1.31 signed format
• Optional output dithering to 24 bit using Triangular Probability Density Function (TPDF)
• Optimized for xCORE-200 instruction set with dual-issue
• Block based processing - Minimum 4 samples input per call, must be power of 2
• Up to 10000 ppm sample rate ratio deviation from nominal rate (ASRC only)
• Very high quality - SNR greater than 135db (ASRC) or 140db (SSRC), with THD of less than 0.0001% (reference 1KHz)
• Configurable number of audio channels per SRC instance
• Reentrant library permitting multiple instances with differing configurations and channel count
• No external components (PLL or memory) required

• Synchronous Sample Rate Converter function
• Asynchronous Sample Rate Converter function

This document pertains to version 1.0.0 of this library. It is known to work on version 14.2.0 of the xTIMEcomposer tools suite, it may work on other versions.

This library depends on the following other libraries:

• lib_logging (>=2.0.0)
• lib_xassert (>=2.0.0)

The following application notes use this library:

• AN00230 - [Adding Synchronous Sample Rate Conversion to the USB Audio reference design]
• AN00231 - [SPDIF receive to I²S output using Asynchronous Sample Rate Conversion]

This following table shows typical resource usage in some different configurations. Exact resource usage will depend on the particular use of the library by the application.

The SSRC algorithm runs a series of cascaded FIR filters to perform the rate conversion. This includes interpolation, decimation and bandwidth limiting filters with a final polyphase FIR filter. The last stage supports the rational rate change of 147:160 or 160:147 allowing conversion between 44.1KHz family of sample rates to the 48KHz family of sample rates.

The below table shows the worst case MHz consumption at a given sample rate using the minimum block size of 4 input samples with dithering disabled. The MHz requirement can be reduced by around 8-12%, depending on sample rate, by increasing the input block size to 16. It is not usefully reduced by increasing block size beyond 16.

This following table shows typical resource usage in some different configurations. Exact resource usage will depend on the particular use of the library by the application.

The ASRC algorithm also runs a series of cascaded FIR filters to perform the rate conversion. The final filter is different because it uses adaptive coefficients to handle the varying rate change between the input and the output. The adaptive coefficients must be computed for each output sample period, but can be shared amongst all channels within the ASRC instance. Consequently, the MHz usage of the ASRC is expressed as two tables; the first table enumerates the MHz required for the first channel with adaptive coefficients calculation and the second table specifies the MHz required for filtering of each additional channel processed by the ASRC instance.

The below tables show the worst case MHz consumption per sample, using the minimum block size of 4 input samples. The MHz requirement can be reduced by around 8-12% by increasing the input block size to 16.

Typically you will need to allow for performance headroom for buffering (especially if the system is sample orientated rather than block orientated) and inter-task communication. Please refer to the application notes for practical examples of usage.

Configurations requiring more than 100MHz cannot currently be run in real time on a single core. The performance limit for a single core on a 500MHz xCORE-200 device is 100MHz (500/5). Further optimization of the library, including assembler optimization and pipelining of the adaptive filter generation and FIR filter stages, is feasible to achieve higher sample rate operation within the constraints of a 100MHz logical core.